Unlike dynamic random access memory (DRAM) and static random access memory (DRAM), a nonvolatile semiconductor memory is a type of semiconductor memory that can preserve stored data even if power has been removed. Nonvolatile semiconductor memories include read only memories (ROMs), programmable read only memories (PROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs, or flash EEPROMs).
A flash EEPROM includes a plurality of memory cells arranged in a matrix of rows and columns on a semiconductor substrate. The flash EEPROM has the capability of simultaneously erasing the entire array of memory cells as well as a subset of cell blocks divided into one or more memory cell rows. The flash EEPROM further offers the capability of electrically programming or reading the contents of one or more memory cells in the array.
Memory cells in the flash EEPROM typically employ floating gate transistors arranged in rows and columns, each having a source, a drain, a floating gate and a control gate. The floating gate, typically comprising polycrystalline silicon, overlaps a channel region formed in a semiconductor substrate, and overlaps edge portions of source and drain regions at opposite sides of the channel region through a tunnel oxide layer. The control gate lies over the floating gate, separated therefrom by an intermediate insulating layer. Control gates of floating gate transistors occupying a same row are connected to a common one of multiple word lines. Drain regions of floating gate transistors occupying the same column are connected to a common one of multiple bit lines. Source regions of the floating gate transistors are connected to a common source line.
A floating gate transistor is programmed by grounding the source region, applying a positive voltage, such as 6 volts, to the drain region, and applying a high voltage, such as 12 volts, to the control gate. The electric field between the drain and source regions causes electrons to accelerate along the channel region, thereby generating hot electrons by impact ionization. The hot electrons gain energy from the high voltage applied to the control gate and are trapped in the floating gate, by jumping through the potential barrier of the tunnel oxide layer. Thus, electrons are charged into the floating gate by channel hot electron injection. As a result, the threshold voltage of the floating gate transistor is increased by the injection of electrons into the floating gate. This increased threshold voltage, for example about 7 volts, causes the floating gate transistor to be nonconductive during a normal read-out operation of the memory.
To erase a programmed floating gate transistor, the control gate is grounded, the drain region is floated, and an erase voltage, such as 12 volts, is applied to the source region. Electrons stored in the floating gate are tunnelled out to the source region by the Fowler-Nordheim tunnelling effect (hereinafter referred to as F-N tunnelling). As a result, the floating gate transistor has a decreased threshold voltage, such as about 2 volts, thereby causing the transistor to be conductive during a read-out operation.
To read data stored in a floating gate transistor, a read-out voltage, such as about 5 volts, is applied to the control gate, the source region is grounded, and a voltage of about 1 volts is applied to the drain region. An erased memory cell, i.e. an erased floating gate transistor, is conductive, and a programmed memory cell is nonconductive. Data stored in the memory cell may be read-out by a sense amplifier adapted to sense the conductive state of the memory cell.
During erasing, if an erase voltage is applied for too long of a period of time or at too high of a voltage level, some of the floating gate transistors may become overerased. A floating gate transistor is overerased when its threshold voltage becomes negative. Once a floating gate transistor has been overerased, it operates as a depletion mode device. Thus, even if the overerased transistor is not selected, it remains in a conductive state. Thus, memory cells sharing the same bit line as an overerased cell are subject to inaccurate reading and programming operations, thereby leading to malfunction of the memory device.
Flash EEPROM cells within a matrix generally do not erase at the same rate due to the deterioration of tunnel oxide layers by variations of process and erase time and programming/erasing cycles. Thus, a distribution of threshold voltages of memory cells may be dispersed. If some of the memory cells are in overerased states or if their threshold voltages are not in the range of reading margins of the erased cells, the flash EEPROM will malfunction.
Techniques have been developed to prevent overerasure of flash EEPROM cells and to converge the threshold voltage distribution of the floating gate transistors to within a predetermined voltage range. An example is disclosed in "Self-Convergence Erasing Scheme For A Simple Stacked Gate Flash EEPROM", IEEE Tech. Dig. IEDM 1991, pp 307.about.310, incorporated herein by reference. The self-convergence erasing technique has two steps. In the first step, the flash EEPROM cells are erased by F-N tunnelling from the floating gates to the source regions by applying -13 volts to the control gates, grounding the drains, and applying 5 volts to the source regions. During the second step, the threshold voltages of the cells are converged by employing avalanche hot carrier injection, in which 5 volts is applied to the source regions with the control gates and drains grounded. The avalanche hot carrier injection causes the threshold voltages of the memory cells to converge to a certain steady-state determined by a balance between the avalanche hot electron injection and the avalanche hot hole injection. However, this technique suffers from a problem in that a high amount of drain-source current flows during the self-convergence erasing step. It also takes a large amount of time to self-converge the threshold voltages. Furthermore, the avalanche hot holes produced in the self-convergence step incur the deterioration of tunnel oxide layers, thereby affecting the reliability and life span of the flash EEPROM.
In an attempt to address the above problems, an improved technique is disclosed in U.S. Pat. No. 5,521,867, incorporated herein by reference. In this technique, the self-convergence step for providing a tighter distribution of the threshold voltages following erasure employs avalanche hot carrier injection by applying 6 volts to drain regions connected to bit lines and a control gate voltage to the control gates connected to word lines. It offers the advantage of an adjustable steady-state threshold voltage by the application of the control gate voltage. However, since the avalanche hot carrier injection is similar to the programming step, increasing the control gate voltage to enhance the self-convergence speed momentarily programs the memory cells, and thereby may cause them to vary outside the reading margin range of the erased memory cells. The control gate voltage could be lowered to mitigate this problem, but reducing the control gate voltage causes a decrease in the speed of the self-convergence. Moreover, the process variation for the memory cells makes it difficult to adjust the self-convergence characteristics. Since this technique employs avalanche impact ionization, it is not able to prevent the flow of current through the channels of the memory cells and the generation of avalanche hot holes. Thus, there is a need for an improved technique capable of preventing the degradation of the tunnel oxide layers due to the hot holes and the consumption of the current flowing through the cells.
A second technique is disclosed in U.S. Pat. No. 5,295,107, incorporated herein by reference, in which the first and second steps employ F-N tunnelling. That is, in the first step, erasure is performed by applying an erase voltage of -14 volts to the control gate for 0.1 sec with the drain region grounded, and by applying a voltage of 5 volts to the source region. Following erasure, in the second step, the self-convergence of the threshold voltages for the memory cells is performed by applying a voltage of 14 volts to the control gate for 0.1 sec with the source and drain regions grounded. Since F-N tunnelling is used, which is slower than the hot carrier injection technique described above, a self-convergence time period of several hundreds of milliseconds is required. To enhance the self-convergence speed, the voltage between the control gate and the substrate may be increased. However, since this would drive the memory cells to a programmed state, such an increase must be avoided. For this reason, use of this technique results in a self-convergence speed which cannot be reduced below several tens of milliseconds.